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Tuesday, May 01, 2012

Interra Systems Bangalore is looking for the Professionals



This job is posted at www[dot]IndiaTechJob[dot]com
Interra Systems Bangalore is looking for the Professionals in following fields:


Job Title: Specman/System Verilog Engineers
Exp Range: All levels

Mandatory Skills: Expertise in either Specman or System Verilog
Knowledge of OVM/VMM/ERM
Experience in test planning, test bench development, stimulus generation, checking, and functional coverage.
hdls - verilog and vhdl

Preferable Skills: Bus protocol knowledge like AHB, OCP etc, serial protococls like uart, i2c etc

Job Description: The individual will be responsible for random verification at IP level in System Verilog or Specman. Would be required to prepare random verification plan and create the radom verification testbench for different IPs/modules. Would need to develop generator, driver, monitor, checker, scoreboard and most importantly functional coverage. Would be responsible to meet 100% functional coverage and code coverage.

Job Title: SOC Verification Engineer
Exp Range: 2-5 Years

Mandatory Skills :SoC Verification Experience in ASM/C, Knowledge of Verilog, VHDL

Preferable Skills: ARM based SOC verification using C, AHB/OCP protocols

Job Description: The individual will be responsible for processor based verification of complex SOCs. Would be required to prepare verification plans and testplans for different IPs/modules at top level. Has to develop and maintain testcases/testsuites and should be capable of pin pointing the RTL code related to the issues/bug being
found. Individual would be responsible to meet 100% toggle coverage.

Job Title Memory Characterization Engineer
Exp Range All levels

Mandatory Skills: Candidate must have transistor level circuit design experience of memories.

He/She should have worked on 65nm / 45nm / 28nm process technologies and must have understanding of design issues related to process.
He/She must have good understanding of memory architecture.
He/She must have good understanding of circuit design concepts for low power CMOS circuits and must have done extensive simulation of memory instances or compilers.Thorough understanding of critical paths and have the ability to debug glitches in design and characterized data and have very good understanding of margins in memories.Understanding of front end memory models generation and validation.circuits.

Preferable Skills :Scripting experience in Perl would be preferable.

Job Description: Candidate is expected to work as individual contributor on memory characterization projects. Candidate must have extensive understanding of memory critical paths and characterization tools. Candidate must have done logic verification of memories using verilog or ESPCV. Candidate must have significant exposure to
validation of the characterized data and undertaken at least few memory compilers or instances. Candidate must have good understanding in generating EDA views of IP libraries. Candidate must have good experience in QA process for release of .libs and models.

Job Title: Memory Layout Engineer
Exp Range 2-5 years

Mandatory Skills :Candidate must have experience in layout design of memory leaf cells and at top level of memories
He/She should have worked on 65nm / 45nm / 28nm process technologies and have understanding of issues like WPE, LOD effects.
He/She must have good understanding of physical verification checks – DRC, LVS, ERC and reliability checks – IR and EM.
He/She must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
He/She must have good understanding of Basics of CMOS circuits. Basic knowledge of skill or any compiler related language would be required.

Preferable Skills: Advanced Skill to develop layout and schematic tiler would be very valuable. Perl scripting expertise would be good to have.

Job Description: Candidate is expected to contribute individually by working hands-on layout design of SRAM/ROM/CAM/Custom memories and physical verification of memories. He/She may also be required to mentor / lead team of memory layout designer. Candidate may be required to interact and work with customer projects at their work place.

Job Title: IP Modeling Engineer
Exp Range 2-5 years

Mandatory Skills Candidate should have good understanding of FE ASIC Design Flow & Methodology.
He/She should also have a fair understanding of CMOS circuit design and low power concepts.
Candidate must have thorough knowledge in Verilog / VHDL and basic understanding of one HV Language like 'e' or System Verilog
He/She must have worked with at least one of the leading simulator such as NC Verilog, VCS, ModelSim,and/or Specman, both at the design level as well as verification level. He/She must have worked on generation of CPF/UPF models for libraries and IBIS models for IOs.
Must be hands-on with debugging GUI tools such as Simvision and/or Debussy.

Preferable Skills: He/She should be good in any scripting languages, preferably Perl.

Understanding of ATPG modeling and flow/tools will be a big plus.

Job Description: Candidate is expected to work as individual contributor on modeling of IOs, Standard cells and memories like single port/dual port/register files/CAMs etc.. Job require to develop models for these IPs, create test benches simulate them. Candidate must have good understanding in generating EDA views of IP libraries.Candidate must have good experience in QA process for release of .libs and models.

Job Title: System C Development Engineer
Exp Range 2 to 5 years

Mandatory Skills: Good understanding of Microprocessor, Microcontrollers, SOC architecture, bus protocols etc.

Proficiency in Systems C, C++ , OOPS, STL, data structures, algorithms and programming concepts.

Experience in developing systemC based models for the virtual platform of a SoC
Strong System C development and debugging skills using popular IDEs/debuggers.
Strong System C development and debugging skills using visual studio 2008/2010 desirable.

Job Description - Be a technical contributor for developing System C behavioral models and software.

- Develop/enhance behavioral models in SystemC.
- Debug and fix the change requests/bugs.
- Develop regressable self checking test suites using C/ARM assembly.

Job Title VLSI CAD Flow Developer
Exp Range 1-6 years

Mandatory Skills: Strong Perl programming experience

Electronics Background

Some exposure to semi-conductor industry and basic understanding of VLSI design Methodology

Preferable Skills: Object-oriented Perl, Tcl, Shell Scripts, Verilog, VHDL

Job Description: Automation of various semiconductor design flows and methodologies

Job Title: RTL Synthesis Flow Development Lead

Exp Range 3-6 Yrs

Mandatory Skills: Candidate must be familiar with CAD flow development and have good understanding on overall VLSI digital frontend methodologies. Perl/Tcl proficiency is required. Knowledge of RTL synthesis is required.
The lead is expected to be an expert in RTL development and logic/physical synthesis using Cadence (preferred) or Synopsys synthesis tools.
Expert working knowledge of synthesis methodology/scripts and tool options is expected. The candidate should have good knowledge of related front-end tools for electrical rule checks and RTL analysis to identify design issues early. Expertise in timing constraints management is a must – this involves both development as well as validating the quality of constraints. Good understanding is required on formal verification.Experience in DFT insertion in RTL and power aware synthesis will a plus.

Preferable Skills: Experience in DFT insertion in RTL and power aware synthesis is also desirable.

Job Description: The lead has to define and develop state or art front end flow with Cadence tools. This will include working with various design teams and defining the specification. Responsibility also includes implementing the flow with developers, deploy and support.

Job Title Physical Design Flow Developer
Exp Range 2-5 Yrs

Mandatory Skills: Encounter, perl, At least 5 full chip tapeouts

Preferable Skills: Detailed understanding on timing analysis and other post layout analysis on Cadence tools will be a big plus. Some exposure on automation including perl is desired.

Job Description: Flow development of Digital backend implementation on Cadence physical design tools.

Job Title Physical Design Engineers
Exp Range All Levels

Mandatory Skills IC Compiler, PrimeTime, At least 5 full chip tapeouts on 65 nm and lower technologies. Detailed understanding on Timing Analysis, Physical Verification, Power Analysis and Reliability Analysis will be required.

Preferable Skills required: Hercules, Calibre, PrimeRail

Job Description - Fully responsible of physical implementation on various process nodes
- Fully responsible of signoff tasks, including power integrity, signal integrity, timing analysis and physical verification

- Coach and resolve technical issues of others


Anyone fulfilling the above criteria can mail their resumes at dhawalbhasin@gmail.com.

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